A MOS solid-state imaging device is generally used as an amplification type solid-state imaging device. The MOS solid-state imaging device includes a pixel section having a plurality of pixel cells which each generate a signal Embodiment 1 according to an amount of received light; a scanning circuit disposed around the pixel section; and a signal processing circuit, where the scanning circuit is configured to read a signal potential from the pixel section.
A solid-state imaging device is known in which a charge pump circuit is formed on a semiconductor substrate on which a MOS solid-state imaging device is disposed, in order to generate a potential higher than the power source potential, or a potential lower than the GND potential.
Japanese Unexamined Patent Application Publication No. 2004-241491 discloses a solid-state imaging device which includes a charge pump step-up circuit for generating a potential higher than the power source potential. FIG. 15A is a block diagram of the conventional charge pump step-up circuit disclosed in Japanese Unexamined Patent Application Publication No. 2004-241491. FIG. 15B is a timing chart illustrating the operation of the charge pump step-up circuit illustrated in FIG. 15A.
As illustrated in FIG. 15A, a conventional charge pump step-up circuit 20a includes a pump unit 201a which charges or discharges a pump capacitor in order to generate a potential higher than the power source potential; a comparator 202a which determines whether or not a potential Vh generated by the pump unit 201a has reached a desired potential; and a resistor potential divider circuit 203a which generates a divided output potential of the charge pump step-up circuit which can be compared by the comparator 202a. 
The charge pump step-up circuit 20a configured in the above manner is driven by a PMPCLK signal which is generated by a clock generator (CLK generator) 22. The electric charge generated by the charge pump step-up circuit 20a is distributed by a smoothing capacitive element 21a so as to stabilize the output potential Vh. Then as illustrated in FIG. 15B, when the output potential Vh of the charge pump step-up circuit 20a reaches a desired potential, the comparator 202a sets a PMPEN signal to Low, which is an enable signal of the pump unit 201a, thereby causing a PMPCLKi signal inputted to the pump unit 201a to be stopped, and thus the operation of the pump unit 201a is stopped. On the other hand, when the output potential Vh of the charge pump step-up circuit 20a falls below the desired potential, the comparator 202a sets the PMPEN signal to Hi, thereby causing the operation of the pump unit 201a to resume. As illustrated in FIG. 15B, the output potential Vh of the charge pump step-up circuit 20a fluctuates up or down from the desired potential in accordance with the frequency characteristic of a feedback circuit including the resistor potential divider circuit 203a and the comparator 202a of the charge pump step-up circuit 20a. 
A charge pump step-down circuit for generating a potential lower than the GND potential has a similar configuration to that of the charge pump step-up circuit 20a. FIG. 16 is a block diagram of a conventional charge pump step-down circuit.
As illustrated in FIG. 16, the conventional charge pump step-down circuit 20b includes a pump unit 201b which charges or discharges a pump capacitor; a comparator 202b which determines whether or not a potential Vl generated by the pump unit 201b has reached a desired potential; and a resistor potential divider circuit 203b which generates a divided output potential of the charge pump step-down circuit which can be compared by the comparator 202b. 
The conventional charge pump step-down circuit 20b operates similarly to the conventional charge pump step-up circuit 20a, and the output potential Vl of the charge pump step-down circuit 20b fluctuates up or down from the desired potential. The electric charge generated by the charge pump step-down circuit 20b is distributed by a smoothing capacitive element 21b so as to stabilize the output potential VI.